The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology
Scan architectures, RT-level scan design, and Boundary Scan (JTAG). Digital System Test and Testable Design: Using ...
Memory fault models, MBIST (Memory BIST) methods, and functional procedures. The book by Zainalabedin Navabi (2010) is a